Frequency synthesizers are commonly used to generate signals of a desired frequency, e.g. in the field of terrestrial communication or satellite communication. A widespread type of a frequency synthesizer is a fractional-N phase lock loop (PLL) frequency synthesizer, which allows for a very high frequency resolution. A typical configuration of such a fractional-N frequency synthesizer is illustrated in FIG. 1. The fractional-N frequency synthesizer 100, according to FIG. 1 comprises a reference clock generator 101, a digital core 102, a phase frequency detector (PFD) 103, a charge pump 104, a loop filter 105, a voltage controlled oscillator (VCO) 106, a divide-by-2 pre-scaler 107, a ⅘ divider 108, an M-counter 109 serving as a fractional-N divider, and an A-counter 110. An output signal of the VCO 106 is pre-scaled by the divide-by-2 pre-scaler 107 and the ⅘ divider 108, and fed to the fractional-N divider 109. In the fractional-N divider 109, the frequency of the signal is divided down by a fractional number N, and the output of the fractional-N divider 109 is fed to the PFD 103. In the PFD 103, a reference clock signal output by the reference clock generator 101 and processed in the digital core 102 is compared to the output of the fractional-N divider 109 with regard to its phase and frequency. The PFD 103 compares e.g. the up- or down-slopes of the respective two input signals and outputs a voltage signal indicative of a phase difference of the respective up- or down-slopes, wherein the polarity of the output voltage of the PFD 103 indicates the sign of the phase difference. In other words, the polarity of the output voltage of the PFD 103 indicates the temporal order of the respective up- or down-slopes. The signal output by the PFD 103 is converted to a current by the charge pump 104, and the generated current is input to a loop filter 105 in which it is integrated to form a voltage control signal for the VCO 106. By the phase lock loop formed by the PFD 103, the charge pump 104, the loop filter 105, the VCO 106, the divide-by-2 pre-scaler 107, the ⅘ divider 108, and the fractional-N divider 109, the output frequency of the VCO 106 is controlled so that the pre-scaled and divided output signal of the VCO 106 has the same frequency as the reference clock signal output by the reference clock generator 101 and processed by the digital core 102.
In the above, the dividing down of the frequency of the output signal of the VCO 106 by the fractional-N divider 109 is achieved as follows. If N would be set to an integer division ratio, the fractional-N divider 109 would output a pulse for every N subsequent pulses input to the fractional-N divider 109. Then, each N-th pulse is fed to the PFD 103, and the division ratio N is fed to the digital core 102, so that the reference clock signal output by the reference clock generator 101 may be processed accordingly. In particular, the reference clock signal is processed so that the digital core 102 outputs a pulse of the reference clock signal only in a timing interval in which also an N-th pulse is expected to be output by the fractional-N divider 109. In other words, by the above configuration, every N-th pulse of the pre-scaled output signal of the VCO 106 is compared to a respective pulse of the reference clock signal. In a simplified example, in which the divide-by-2 pre-scaler 107 and the ⅘ divider 108 are omitted, the frequency of the output signal of the VCO 106 in this manner is controlled to be equal to N times the frequency of the reference clock signal output by the reference clock generator 101.
Fractional division ratios may be obtained by alternatingly setting the fractional-N divider 109 to different integer division ratios. For example, a resulting/desired division ratio of 10.5 may be obtained by alternatingly setting the actual/momentary division ratio N of the fractional-N divider 109 to 10 and to 11. According to a further example, a resulting division ratio of 10.1 may be obtained by setting the actual division ratio to 11 for one out of 10 cycles of the fractional-N divider 109, and to 10 for the remaining nine out of 10 cycles. Of course, more elaborate schemes for setting the integer division ratios may be employed, such as for instance a scheme in which the relative occurrence of integer division ratios is determined by a distribution such as a Gauss-distribution centered on the desired fractional division ratio. Accordingly, in the example in which the fractional division ratio is desired to be 10.5, integer division ratios 11, 12, 13 etc. with decreasing relative occurrence, and integer division ratios 10, 9, 8, etc. with decreasing relative occurrence may be set.
With a fractional-N frequency synthesizer as described above, however, the problem occurs that the two signals that are compared at the PFD are never exactly in phase. That is, in a cycle of the fractional-N divider 109 in which the actual division ratio of the fractional-N divider 109 is set to an integer value below the desired fractional division ratio, the reference clock signal lags behind the output of the fractional-N divider 109, whereas for a cycle in which the actual division ratio the fractional-N divider 109 is set to an integer value above the desired fractional division ratio, the signal output by the fractional-N divider 109 lags behind the reference clock signal. Accordingly, the output voltage of the PFD 103 frequently changes polarity, so that also the current to be output by the charge pump frequently changes polarity. However, on occurrence of a flip of polarity of the current, the current is momentarily very small, and due to the characteristics of the charge pump 104 the magnitude of the current changes non-linearly in this regime. Also, the time dependence of the output current is unpredictable in this case. For this reason, this regime of the charge pump 104 is referred to as “non-linear zone” or “dead zone”. This non-linear change of the magnitude of the current output by the charge pump 104, and the unpredictable time-dependence influences the VCO 106, so that the output signal of the VCO 106 comprises unwanted spurious frequency components referred to as “spurs”. Since these spurs are due to the operation of the fractional-N divider 109, these spurs are referred to as “fractional spurs”.
Fractional spurs occur if the desired division ratio N is close to an integer or close to a half-integer. It is found that fractional spurs occur for approximately 16% of the frequency space of the output signal, or respectively for approximately 16% of the space of desired division ratios N. Thus, in the following, desired division ratios N that are in the interval n−0.05<N<n+0.05 or in the interval (n+½)−0.05<N<(n+½)+0.05, where n is zero or a positive integer, will be referred to as “spur critical”. Desired division ratios N that are not in these intervals will be referred to as “spur free” values.
Further sources of spurs are the coupling-back of the output signal of the VCO 106 to the reference clock signal or vice versa, especially if the frequency synthesizer is realized in a single-chip configuration, a potential charge pump mismatch or a potential charge pump leakage.
In the prior art, different mechanisms to reduce the level of fractional spurs are known, and include dithering, noise shaping in the PFD, and applying an offset current (bias) to be charge pump, wherein the latter will suppress fractional spurs at the price of an increased phase noise. However, neither of these mechanisms is known to completely remove fractional spurs. Also, especially for fractional-N frequency synthesizers implemented on a single chip, means for reducing the level of fractional spurs are limited due to design considerations and space limitations.
Publication “A wideband 3.6 GHz digital DS fractional-N PLL with phase interpolation divider and digital spur cancellation” by Zanuso, M. et al., IEEE Journal of Solid-State Circuits, Vol. 46, No. 3, March 2011, pages 627-638, discloses a fractional-N frequency synthesizer, in which the PFD is replaced by a time-to-digital converter (TDC) and which employs a phase-interpolator-based fractional-N divider. However, reducing the level of fractional spurs by means of a phase interpolation divider will increase phase noise, and active loop filtering is required.
Also, hybrid fractional-N frequency synthesizers are proposed in which the frequency of the reference signal may be adjusted such that spur-critical values of the division ratio N may be avoided. In such hybrid fractional-N frequency synthesizers, the reference clock signal is provided by a direct digital synthesizer (DDS), for which the output frequency may be tuned. In the DDS, a pre-stored signal sequence (e.g. a sine wave) is sampled with an adjustable sample rate, and the resulting sequence of signal values is subjected to digital-to-analog conversion to generate an output signal of a desired frequency. Therein, the desired frequency depends on the sample rate. However, due to sampling errors and digital-to-analog conversion, the output signal of the DDS is not spur-free. Accordingly, also the output of a hybrid fractional-N frequency synthesizer is not spur-free.